Toastie

Wait - any Vogons close by? I shall get my towel and 5 pints of stout (don't like lager that much) ready. All the best Thorsten

Welcome!!! That will be fun! Just make sure that you have a photo/document hosting site for your stuff. EB is not designed to upload such items. Text, yes, but volume stuff like pictures, no. Link these items here and all is good. Looking very much forward to your contributions, questions, proposals, etc. All the best Thorsten P.S.: Nice car!

Any chance, that we can meet in person? This is so cool. I need to digest this, order chips and put it together. Just for the fun of it! Thanks a million (again) for teaching these things. In your courses, I would be a student, reading your lips, even at 8 o'clock in the morning. I have to admit that I skipped 8 o'clock 1st year PChem classes regularly - now I teach these Yours Thorsten

Hi Jo, oh, this looks so elegant ... but I am slow - and need more "input": With pulse you mean an L/H slope, right? So upon startup, both inputs are L? The propagation delay through the OR/AND gates needs to be sufficient for the correct clocking of data, right? This circuit means that I need two shift registers (SR), as I need access to two separate clock lines, correct? And finally: This gives me three outputs on SR 2, so I'd need two SRs for 6 outputs, correct? I am sorry for not getting it right away. All the best Thorsten

Now that's an idea - however, it looks more like a Mafia funeral then. When I see any "pure" Technic car, it looks to me as it was under prolonged machine gun fire; all occupants dead

Yes, works. This one does it as well and saves some variables Best Thorsten

Rocher Percé? Have a nice vacation time!!! Best Thorsten

@Bliss WOW!!! The bit operators make Blockly my first choice for controlling Interface A!!! I already clearly saw its potential when tinkering with this pulsing, shifting, and latching stuff. Mainly because I could a) literally "see" the (critical) code like a flow chart and b) swiftly shuffle around blocks representing otherwise a good number of code lines - sometimes arbitrarily trying out things without losing it Thank you so much! I really like your proposal regarding a plain USB2TTL adapter + two SRs/latches very much. Using discrete TTLs or CMOS chips, this would indeed represent a new and era-correct addition to the line of IntA interfaces we have for the vintage machines: The connection to a modern computer is just done by the USB2TTL conversion of two classical serial lines! Furthermore, if we go full USB serial baud rate, even PWM provided by TC Logo running in a DOSBox-X instance could flawlessly work. @alexGS did patch TC Logo into a serial variant. This version worked "almost" flawlessly with an Arduino as serial-to-parallel converter using DOSBox-X, as documented in the 9750/9771 thread. But it did not find @evank's approval because of the Arduino in-between. With just a USB converter, we can try to convince him, that this is indeed an era-correct approach I did actually play with that idea - but was running out of SRs - I have only one All the best and thank you again!!! Thorsten

Firstly, thank you so much for taking a look at my rookie code! And once more, I missed that. I need to improve! Absolutely agreed on. One of the challenges I like so much though, is using (as @evank makes the rules here ) "era correct" technology. You know, it is so easy to "chicken out" with e.g., Arduinos providing nearly "unlimited" I/O ports; but the real deal is using the stuff available back then. If possible at all! And that is the banger. I was looking for/at that, but I simply can't envision how to make such a device. That indeed would be the true "era correct" connection between now and then! All the best, and let us rock and roll these efforts! Thorsten

Why is that? This is so cool to read - 400000 km - incredible. And of course absolutely sustainable, this car was built using resources which are still in use. So cool. Best wishes, Thorsten

Or out of ROM? Best Thorsten

IT WORKS I mean one possible Compis J5 <-> IntA 2/4 wire “solution”. Just to reiterate/get you back on track: The Swedish school computer "Compis" controlled Interface A via a cable with a 6 pin DIN plug on one side that - well - plugged into a 6 pin DIN socket named “J5” on the Compis. On the other side was the usual 20 pin ribbon connector for Interface A, however, as new footage proves, with a rather bulky box attached. Paul Findley (@amine and @evank also know) has taken some photographs of the Compis cable for the 9750: According to the Compis schematics, the DIN socket contacts are wired internally to +5V, GND, in_0, in_1, out_0 and out_1. The in/out lines are connected to an 8255 PIO. Its ports are programmable, but I left that out of the equation and assumed they are (directionally) “fixed”. So how do 2 (TTL/PIO) outputs control 6 Interface A outputs? Obviously, this must be serial in some way. Recall that we are in Big Brother’s year 1984 or even before - 1984 was the year when the Compis computer was officially rolled out to schools, as far as I know. Serial-to-parallel is as old as serial and parallel are. So a quick check on my beloved 74XXX TTLs and CD4XXX CMOS chippies told me: It's all there, even before 1980 ... My storage facility here had a 74LS164 (8-bit parallel out serial shift register (SR) in stock. However, these do shift = clock-through the 0/1 data coming in, so the outputs flicker accordingly, until all 8 bits are in. No problem, when you do that on the micro seconds temporal scale. This needs a microsecond clock of course, and I believe a decent machine code program can do so using the 8255 ports. So that could be all what is needed: A 74LS164. Plus maybe a 100 nF blocking capacitor. But to demonstrate this approach, I didn't have a Compis, nor a computer equipped with a 8255 for I/O. And: I wanted to go full educational (i.e., teaching myself basic digital electronics). So the computer is my Dell laptop, the interface mimicking an 8255 is an Arduino Uno loaded with the USB2Parallel software @Bliss provided, and the programming language is LEGO Blockly, again @Bliss' work - available freely and discussed here on EB in its own thread. This is the plan: On the Arduino's 20 pin Interface A compatible output, I am using only 4 lines: +5V (pins 1+3), GND (pins 5 to 19), out_0 (pin 6), and out_1 (pin 8), for mimicking the two output ports of the 8255 in the Compis. I wanted this to be fully independent of the clock rate for the shift register, be it 1 Hz so I can actually observe what is happening, or as fast as Blockly can go. Or even in situations, when clock rates change during 8-bit data submission, or running at full-speed MHz machine code rates. This rules out a constantly running fixed frequency clock. I didn’t want any output flicker on Interface A – at low clock rates, this could be nerve and model wrecking. In other words, a latch is required. 74LS273 is my friend, a (pos. edge) triggered 8-bit D latch. Sounded good, but turned out to be a little tricky: When 6 bits are in the SR, the latch needs to be triggered. But there are only 2 lines available: Data and clock. Solution: Use SR output #7 (G) to trigger the latch. This requires the introduction of a small delay though, as all 6 relevant SR outputs have to fully settle before the latch is triggered, otherwise wrong readings are latched in. As the latch wants a positive slope, output G needs to transition from L to H upon the 7th clock pule – at that moment the 6 SR outputs A-F are also clocked in and then subsequently latched in. Delay solution: Exploiting signal propagation delay. Six 74LS04 NOT gates cascaded (resulting in an about 70 ns delay) did do the trick, but there is more, there always is: When using the SR to provide the pos. slope latch clock, the SR needs to be reset for the next serial data loading, as arbitrary pos/neg bits of the last loading are still present in the SR and will trigger the latch on each pos. slope, i.e., every 0/1 sequence coming through upon next 8 bit load. As there is no additional clear line available, I used the SR again: Solution: Connect SR output #8 (H) via a further NOT gate to input “clear” on the SR. Composing an 8-bit serial data packet accordingly, assuming the SR was cleared before (outputs A-H = 0), looks like this: Bit #1 is always 1 and loaded into SR upon clock tick 1. This will show up on output G upon clock tick 7, is then running through the delay line and fires the latch. Bits #2 to #7 = data bits. Clock ticks 2 to 7. All 6 data bits are present, and the latch triggers after delay. Bit #8 may be L or H: It is just used to shift bit#1 into SR output H, which is inverted via a NOT gate and resets the SR. The latch outputs remain unaffected and thus stable Interface A outputs are guaranteed. Here is a schematic (I know, I’ll get flak from @BrickTronic for the wrong a’s in the IC numbering - I am still too dumb to get it right in Target 3001). I am also absolutely sure that this can be done much more elegantly, I am thinking about 74LS595, but don’t have one. There are for sure better ways of doing this. @BrickTronic pointed me already to CD4094 - that is a nice one as well. The LEDs are purely for optical inspection of the 8 outputs of the SR and the 6 latch outputs. In addition, I used the LEDs for serious debugging, particularly software ^^ ... Note about the cascaded NOT gates for establishing the 60-100 ns delay between the SR clock and latch clock: 6 TTL NOT gates (74LS04) were sufficient, but inverting the SR H output for resetting the SR would need another TTL IC. Well, the good old CD4000 CMOS chips have much longer propagation delays, and some are fully compatible with the TTL world: CD4069 (6 NOT gates) is. So two NOT gates of CD4069 in series provide an about 100 ns delay, safely ensuring proper timing. And reducing the IC count required to running this setup by one, as 4 NOT gates are still available, one used for the SR output H – SR clear connection. Alternatively there is 74LS123, (two mono-flops) will definitely work as well. Also note that I did not use the HC version but the LS version of 74164; but Target had only a "poor" schematic for the LS version. Further note that the InterfaceA inputs (pins 18, 20) may also be latched by connecting them to the D7+8 inputs of the latch and routing the outputs Q7+8 of the latch to the Compis side inputs. However, this would require an output write cycle (whether outputs changed or not) to update the latch for updated input reading. This is exactly what TC Logo does at a 1 ms rate on an IBM XT. But its optional; once your computer is talking/listening to 9750 through a PIO (or any other peripheral I/O device separating the data bus from the outside world), parallel input latching is essentially luxury. The setup shown above runs really stable with the LEGO Blockly program shown below; it counts from 0 to 63, creating all possible Interface A output states. Really fast with no delay, sometimes apparently yielding swiftly to other Windows processes. With delay, one can study the SR vs. latch clocking. The left red LED never lights up visibly, as the reset process is too fast. Here is a photograph - as you can see, I am using only 4 lines of the 20 pin connector: +5, GND, out_0, out_1: I am fully aware, that @Bliss will tear my decimal to binary conversion to shreds, I am simply a novice regarding LEGO Blockly. This is what I came up with to count from 0 to 63, convert each decimal number into binary and wrap a leading and trailing bit around the binary number: I have learned a lot about shift registers, timing of such devices, and handling latches in such an environment - particularly when you don't have more than two control lines. As @BrickTronic says: There are many ways to ROM, uhm Rome. Finally, here is another of my crappy videos showing the dynamics of SR shifting/latch loading. First 5 seconds: Max Blockly speed shifting/loading of numbers 0 to 63. Remaining plus 60 seconds: ASMR version of shift register loading and latch clocking for the same cycle, delayed by one second for each clock step in the Blockly program: https://bricksafe.com/files/Toastie/compis-and-9750/Compis Serial to parallel.mp4 It is on BrickSafe - as it is too lame for YT. When I hover over the link the video starts. Best wishes Thorsten

Hi Jo, exactly as I have done - and it works. I am just composing the corresponding post in the 9750/9771 thread and will tag you, if you find the time, you may want to check whether I screwed up things again Thanks a lot + all the best Thorsten P.S.: I looked into CD4094 - that is indeed a >nice< chip! Reminds me of 74LS595 ... I am sure they will work as well in some way with only two lines for clock and serial in using one of the outputs maybe for strobe ...

Hi Jo, thanks again for checking!!! I already corrected my post above, it is of course a 74LS164 I am using. Sorry for the confusion!!! Will post details tonight in the 9750 thread. I shall also take a close look into CD4049, which I don't have though (as of now). All the best, Thorsten

@Bliss, I still did not play with the ToyPad blocks - that is on my agenda for the coming days. I see the pad as a very cool I/O device, as I am also having a couple of the tags (but never ever played Dimensions - I am a total nerd) because a) I liked the figures that came with them and b) these expansion packs were essentially "thrown out" of some stores - I even forgot when that was. What I did in the meantime was figuring out how the 4 pins (plus 5V and GND) of the I/O terminal of the Swedish Compis school computer could drive 6 IntA outputs (and read two inputs). The Compis was endorsed by TLG for operating IntA in the classroom; they made corresponding CP/M-86 LEGO Lines software. Hardware wise it must have been serial of course. Back in the 1980's, SIPO chips (e.g., 74LS164, 8 bit shift register, SR) were all over the place. So I managed to put together a simple SR+8bit latch circuit that does the trick with only two input lines: Clock and serial data. Which fits well with the two outputs of the Compis coming from a 8255 PIO driving 6 IntA outputs. And - I used your LEGO Blockly to demonstrate that it works! That was fun. I should maybe post that stuff soon here on EB. During my programming efforts, I came across some challenges (which are caused by my limited knowledge, of course): I was unable to find "bit-manipulation" operators, such as bit-wise AND/OR etc. Is that correct? I believe that the boolean operators you already provided (AND/OR) are for logical comparison? There is the "remainder of" block, but no "integer" block - for the latter I used the "round down" block, that should be equivalent, right? Is there a "2 to the power of x" block? I am asking solely because I am using these operators/functions quite often in BASIC or C when it comes to bit manipulation. I have the impression that all the "vintage" LEGO devices (IntA/B) are more easily operated using the dual system :D. The same holds true for the RCX and other vintage PBricks, as they hold, e.g., the motor status information frequently within (bit) registers. For the demonstration of my Compis experiment, I wanted to run a loop cycling through the (decimal) numbers 0 - 63 (000000 to 111111) and switch the outputs of IntA correspondingly. I need to do that bit-wise, as the access to IntA goes through serial-to-parallel conversion. This is what I did for the dec to bin conversion - is it remotely what I should do? It works well, but it is most probably - at best - clumsy. Forget about the two left functions and the leading/trailing ON/OFF commands in the conversion loop as they are entirely hardware related: First, out_0 = clock is set to 0, then a data bit is set via out_1 (0 or 1) and then the clock is set to 1 as the SR (74LS164) wants a pos. slope to clock-in the data bit present at its serial input): Thank you very much for looking into this! All the best Thorsten