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  1. This thread is about one of the first attempts of TLG wandering into the world of electronic control using actuators and sensors in connection with a computer. Whoever wants to contribute, feel free to dump it in here. Should there exist already a similar thread on EB, moderators please let me know, merge, or delete this thread! Here are absolutely wonderful references to already elaborate documentations and solutions for the operation of "TC1 world 4.5V machinery": Apple II operating 9750 and much more: Reengineering procedure and functionality of 9771 (in German); schematic of LEGO Interface 1 ISA bus card 9771: Details on the operation of 9750 with “semi-modern” computers using the parallel port along with Windows-based executables: On the Internet Archive: (TC1 and ControlLab) (TC1 and ControlLab) And finally a tutorial style written 300+ page wonderful book about the PC hardware, beginning with the architecture of an IBM PC upto the Pentium CPU level, including the ISA bus organization and its signal timing: (Please add more to this list - I have already lost track here ...) Introduction In the 1991 LEGO (dacta) book “Technic Control 1 Resources Guide” (TC1RG), the introduction reads: “Welcome to the world of Technic Control 1 (TC1) Technology! With TC1, students from middle school through high school can work in a hands-on problem solving environment to understand better the role of computers in today's technology.” The LEGO hardware was released about 5 years earlier. As I am constantly confused with the names as well as set/item numbers TLG is using and as these LEGO Technic Control 1 sets were mostly designed for educational in-class activities (LEGO dacta) and identical “normal LEGO” and “LEGO dacta” items have different item numbers, I am using the names and numbers found in the TC1RG: #9750 = “Interface Box” #9771 = “MSDOS Interface Card” Operation of 9771 This first post discusses the MSDOS Interface Card, as I still don’t own the Interface Box – should be on its way though. The Interface Box, as per references above, features 6 x 2 TMP3055 (TMOS power field effect transistors, 60V, 12 A each ... TLG didn't mess around these days) equipped drivers for digital = on/off operation of 4.5V motors and lights, as well as two op amp driven amplifiers for digitalization (on/off) of sensor signals, touch and light. There is no A/D converter present, all states of the box are of binary nature. The MSDOS Interface Card is an ISA bus data exchange card, which allows to write to 6 latched outputs (on/off) and/or read from two latched inputs (on/off), connected to the Interface Box with a 20wire ribbon cable. The latched information is accessible via the ISA bus IOR/IOW request, respecting DMA priority. Address decoding is done with a simple TTL logic gate assembly; data in- and output is via two 8-bit transparent D flip-flop latches. This assembly is briefly described here. The schematic was already published in 2014 (as noted by @BrickTronic , thanks again!!!) – I just did not find that one. I guess the bizarre naming was confusing Google as well … I just finished reading the entire thread (about 70 entries) on the 2014 www.elektronik.kompendium forum page (referenced above) – and I am very happy that I can fully confirm the findings from more than 8 years ago (oh man) Yes, the card address is 925 (0x39D) with the bridge installed (default) and 926 (0x39E) without. Yes, one can use QBasic to control the card, however, at low speed. There is actually a scanned original LEGO program listing in the thread! It always feels - hmmm - weird to having successfully reinvented something. On the other hand, I discovered this way that I can still comprehend simple TTL logic – I did that more regularly 40 years ago as my hobby (yup nerd throughout my entire life) I also learned that in 2014, one individual from Holland, who earlier found many of the 9771 cards abandoned in the school he was working then, still had one card in 2014 he obviously did not want to sell. He helped a lot with tracing the board and thus for Frank’s final success of reproducing the 9771; Frank only had photographs of the card. Hidden traces were giving him headaches … Now call it a coincidence – a box with 9771 in it, arrived two weeks ago from Holland at our house – and yes, name sounds very familiar … Oh my the world is really small … Most importantly I basically just paid the postage for that package plus a >modest< amount of money. This individual is still responding to EB PMs - it is simply wonderful. So you may ask, why creating this thread at all then? For one, the elektronik.kompendium forum is in German (yes, I have heard about Google translator). Second I had a “hard time” (OK, it was fun) to find the relevant information on 9771 in the over thread 70 entries there. But most importantly: Maybe others have more information/references on "TC1 world" they may want to share here. Here is the schematic, my version that is. Frank’s 2014 version focuses (naturally) on card reproduction, mine on understanding the logic of the device, as I don’t need to make one: The schematic I am aware that many of you guys know how it works (duh); this is more for documentation purposes (for me). I am using this notation: X# means X = L to be true. X[n:m] means from X=n all the way down to X=m. X[n] = single number. X = address, output, input line, or other signal line. ISA_A[ ] = ISA address bus; ISA_D[ ] = ISA data bus, LIA, LIA[ ] = LEGO Interface A bus. 74LS373 8-bit transparent latches: These are eight D-type flip-flop (FF) latches. The FF outputs are each connected internally to a non-inverting TTL driver with output Q, which can be in three states: L, H, high-impedance or tristate. The latter simply means that the driver is “not present” on the bus at all, so it does not affect anything happening there. C input: When input C = H, all 8 FF outputs mirror the logic level present at the D inputs in parallel. When C goes L (on the neg. slope), all logic levels on the D inputs are latched and then remain constant on the FF outputs until C = H again. (As a side note: 74LS374 are not transparent; they sample the D input only upon a positive slope occurring at the CLK input). OC# input: When OC# = H, then the TTL drivers connected internally to the D FF are in tristate. The D FF still do their work though. When OC# = L, the Q outputs have the logic level of the latched D FF information, either L or H. IC_5 (74LS373) OC# is hardwired to GND = L; thus the Q outputs have always a defined logic level, L or H. Q[6:1] are directly connected to the 6 input lines of the 9750 interface box. When the correct address is present on the lines ISA_A[9:0] AND ISA_AEN = L (the PC’s DMA controller is not using the A or D bus) AND IOW# = L (CPU signals an IO write request), the C input on IC_5 = H. This means that the logic level of the 8 ISA_D[7:0] data bus lines are mirrored to the corresponding Q outputs and thus the 9750 box via the LIA bus. When IOW# = H, C goes L and the 8 data bits from the ISA bus are latched and remain present on the Q outputs: 9750 turns on/off the corresponding drivers in the box and thus lamps or motors. Note: The outputs Q[5:4] are not used at all (nc), nor are the inputs D[5:4]. IC_4 (74LS373) OC# is not hardwired to GND, it is directly connected to the C input. In essence, the outputs of IC_4 are only in a logical defined state (L/H) when an IOR# request is issued by the CPU: When the address is correct, ISA_A[9:0] AND ISA_AEN = L AND IOR# = L, then OC# and C go from H to L. Which means that the two inputs D[5:4] of IC_4, which are connected to the two output lines of 9750, are both latched and become visible on the ISA data bus. Furthermore, as the remaining 6 D inputs D[8:7, 4:1] of IC_4 are connected to the corresponding outputs Q[8:7, 4:1] of IC_5, the current input settings on the 9750 box (status of the box drivers = motor, lamps) are also present on the ISA data bus. The CPU thus reads the status of all 8 active 9750 lines (2 inputs, 6 outputs). IC_1 (74LS30, 8-input NAND), IC_2 (74LS27, 3x 3-input NOR), IC_3 (74LS86, 4x 2-input exclusive OR) These three ICs are wired as a logic network to a) decode the address bus ISA_A[9:0], check for DMA access on the ISA_A/D bus, and detect the IOW#/IOR# request of the CPU. Although the I/O address range of an 8088 CPU is 64k (&0000 to &FFFF; the memory address range is 1M, &00000 to &FFFFF), only 10 address lines are decoded by the 9771 card. This should be taken into consideration when doing super fancy programming in the upper IO address range of the 8088 CPU, as the card will not only respond to its default addresses (&39D, &39E), but also to all addresses with a non-zero A[15:A10] signature, regardless what this signature is (all L for &39D/&39E). On the ZX Spectrum this really was a nightmare, as IO address decoding was restricted to only a few internally well encoded addresses. Specific address decoding The card address is mainly determined by IC_1, the 8 input NAND gate. ISA_A[9:7, 4:2] are directly connected to the inputs of IC_1. The output of this gate will only = L when all inputs = H. ISA_A[6:5] are connected to IC_2b (NOR), which means that the output of IC_2b only = H, when all inputs = L. This results in: The output of IC1 will only = L, when ISA_A[9:7] = H and [6:5] = L and [4:2] = H and the remaining third input of IC_2b is also = L. This input is “prepared” by IC_3a+b (XOR): Case 1: Bridge is installed. This pulls the inputs of IC3_a[2] and IC_3b[4] = L. XOR requires the inputs to be of opposite logical level to become H. The output of IC3_a is directly connected to one input of IC1, thus needs to be H for correct address detection; as IC3_a[1] is connected to ISA_A[0], it needs to be H. The output of IC_3b is connected to the remaining input of IC_2b (NOR). As all NOR inputs need to be L for output = H, the input IC_3b[5] = ISA_A[1] thus needs to be H for correct address detection. This all results in ISA_A[A9:A0] = H H H L L H H H L H = 1110011101 = &39D = 925 for correct address detection, i.e. the output of NAND gate IC1 = L. Case 2: Bridge is removed. This pulls the inputs of IC3_a[2] and IC_3b[4] = H. With the same logic as above, this results in 1110011110 = &39E = 926. Further handling of ISA_IOW# and ISA_IOR# is done by IC_2[a,c] (3 input NOR gates). The outputs are only = H when all inputs are L. IC_2[a]: Output of IC_1 = correct address = L and ISA_AEN = L and ISA_IOR# = L (valid CPU IO read request). IC_2[c]: Output of IC_1 = correct address = L and ISA_AEN = L and ISA_IOW# = L (CPU IO write request). The two remaining gates IC_3[c,d] are wired as inverters to match the OC# and C input logic of the 74LS373 latches. And that’s basically it. Lots of words for nothing much. There must be many errors in the text above – I’ll try to wipe them out, so frequent edits may occur. Once again this is for documentation purposes only. Once I finished such a project, I forget almost everything about it within days. By the way, on another note :D - During the annual PTChem lab cleaning frenzy this surfaced: As no one had interest in these mostly TTL chips, as well as CPUs, memory chips and other stuff – I "rescued" them from being trashed. The hardest part was to organize them in some sort of way. What helped me in doing that was this book, I purchased in 1979, one year after it was published; it organizes the more than 2200 TTL-, DTL-, ECL-, CMOS-chips (among some others) listed, into the categories: G = gates, F = flip-flops, M = multiplexers/demutiplexers, Mf = mono-flops, Z = counters (guess why ;). Among the "Gs" is even a 74LS133 – a 13 input NAND gate. I’ve never heard before of such a TTL chip – it makes perfect sense for address decoding :D Yes, I am happy Next: As I don’t want to fry the 9771 card, I am planning to hook up a TTL driver (74LS06 or so) to the outputs of 9771 and illuminate some LED’s using QBasic. Will report here. Best regards, Thorsten